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Testing Loaded Boards

As for bare boards testing is necessary also every loaded board needs to be checked for manufacturing faults. Basically there are three major test methods:


Functional Testing

In the beginning, it was sufficient to do a functional test to check an assembled board. Applying this classic method, the board is connected to the test system via the edge connector. The test system simulates the peripheral systems and checks the board for correct functioning only. The result is a simple GO/NOGO message, i.e. no information about the fault location is provided nor is the fault type indicated, e.g. wrong component, short or stuck-at 0/1.

With the advent of In-circuit test in the late 70's, functional test seemed doomed as In-circuit test promised easier and faster programming and diagnostics. But today, In-circuit testing has a major problem - access. According to NEMI (National Electronics Manufacturing Initiative), nodal access will be virtually nil by the end of 2003. So if no access becomes a reality, it means little or no In-circuit test, which makes functional testing important again. However, like In-circuit test, technology and PCB design can hinder test coverage. And while there have been major advances in the software environment for program preparation that help overcome some of these difficulties, there are still pitfalls to avoid and advance preparation required to succeed in implementing functional testing.

On the surface, component density does not appear to be an issue for Functional Test. After all, the primary concern here is basically "Something goes in, the right information comes out". While admittedly simplistic, this is often the case. Defined stimulus is applied to the inputs of the UUT (Unit Under Test) , and a specific data set should come out of the UUT at the appropriate time. Access to the I/O connectors should be the only access issue. But component density will be a factor. Looking at the pictured PCB , questions have to be answered like;





  • Will access to the circuitry for calibration be necessary?
  • Are diagnostics down to the component or particular area of the UUT critical?
  • If the answer to the previous question is "Yes", will probing be performed by a human or some robotic means?
  • Will automated handlers be used?
  • Are the I/O connectors used easily probed or connected to? If not, is the connector a through hole mount that is accessible via a bed of nails?

There are many levels of automation of the functional test and this level is determined by a lot of factors. Obviously, all of these factors mean that there's no one all round solution. There are options like bed-of-nails, fixtureless flying probe testing, on-line systems with conveyor systems, off line testing, etc.


In-Circuit Testing

Electrical in-circuit test is used to verify the electrical integrity of devices on a finished printed circuit board. The term ICT covers a variety of techniques, all of which rely on physical access to electrical nodes on a board.

A variety of ICT techniques can detect and isolate electrical defects. Shorts testing algorithms quickly check board impedances to detect and identify low impedance (i.e., shorts) between electrical nodes. Analogue in-circuit tests are guarding techniques to measure the resistance, capacitance or inductance of devices, and to verify the orientation and function of diodes and transistors. Digital in-circuit techniques force digital states on device inputs with overdriving techniques (using high-current drivers), and measure the response to verify proper device operation. Additional software and hardware tools assist digital in-circuit tests in easily testing boundary-scan or Flash RAM devices.

ICT also includes powered analogue and mixed-signal (analogue and digital) tests, as well as vector-less test, which uses analogue device characteristics to electrically verify solder joints on complex ICs without requiring knowledge of a device's operation. Unpowered ICT is limited to shorts, analogue in-circuit and vector-less test.

When a manufacturing area requires more comprehensive measurements and process feedback, unpowered ICT fits well. Full ICT systems have become the industry workhorses because of their comprehensive test coverage, pin-level diagnostics and high test throughput. For environments where nodal access is limited or dropping, ICT can be combined with other technologies, such as Automated X-ray and Automated Optical Inspection, to provide a high degree of fault coverage with excellent diagnostics and process feedback.

Boundary Scan

The narrow raster and latest chip technologies get the in-circuit test into severe trouble. Bed-of-nails are not available for these chips due to the narrow raster or the pins cannot be accessed from above at all (e.g. BGAs). One solution could be the installation of test pads on the board, yet this foils the advantage of a reduction in the necessary space due to highest integration. Here the idea of Boundary Scan comes in.

In 1985, a group of European companies formed Joint European Test Action Group (JETAG) to tackle the problem of the limitations of In-circuit testing. It called for incorporating hardware into standard components (controlled via software), eliminating the need for sophisticated in-circuit test equipment. By 1988, the concept gained momentum in North America and several companies formed the Joint Test Access Group (JTAG) consortium to formalize the idea. In 1990, the Institute of Electrical and Electronic Engineers (IEEE) refined the concept and created the 1149.1 standard, known as IEEE Standard Test Access Port and Boundary Scan Architecture.

Boundary scan is a methodology allowing complete controllability and observability of the boundary pins of a JTAG compatible device. It results in the fact that the bed-of nail adaptation getting more and more difficult is dropped but the advantage is maintained, i.e. the testing within the circuitry. Generally speaking, boundary scan means the transformation of the outside nails of a bed-of-nails adapter into inside ones, the so-called "electronic nails". They are provided at the silicon's periphery (at the "boundary").




The theory of boundary scan technology is quite complex and extends the scope of this area. More information can be found on www.sun.com.

 



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